1. Field of the Invention
This invention relates generally to oscillator circuits, and more particularly to on-chip microprocessor oscillator circuits used in clock distribution.
2. Description of Related Art
Planar inductors and inductance capacitance (LC) filters have been implemented in semiconductors using a variety of substrates. N. M. Nguyen and R. G. Meyer, in "Si IC-Compatible Inductors and LC Passive Filters," IEEE Journal of Solid-State Circuits, Vol. 25, No. 4, pp. 1028 to 1031 (1990), which is incorporated herein by reference, describe inductors and LC filters fabricated in a production silicon bipolar integrated circuit processing. Nguyen and Meyer describe how to implement a spiral planar inductor that can be used for high-frequency on-chip filtering, inductive peaking of high frequency amplifiers, and impedance matching for low-noise amplifiers.
J. Craninckx and M. Steyaert, in "A 1.8 GHz Low-Phase-Noise CMOS VCO Using Optimized Hollow Spiral Inductors," IEEE Journal of Solid-State Circuits, Vol. 32, No. 5, pp 736-744 (1997), which is incorporated herein by reference, explain how to extend the use of a spiral inductor to complementary metal-oxide silicon(CMOS) circuitry. FIG. 1 is a block diagram of a phase-locked-loop(PLL) based frequency synthesizer 100 as presented by J. Craninckx and Steyaert for radio-frequency telecommunications.
A voltage controlled oscillator (VCO) 103 generates an output signal having a frequency fOUT. The output signal is fedback to prescaler 104 which in turn divides signal frequency fOUT by a predefined amount. The resulting signal with frequency fDIV is one input signal to phase detector 101. The other inputs signal to phase detector 101 is a signal with a reference frequency fREF.
In response to the two input signals, phase detector 101 generates a phase correction signal that is filtered by loop filter 102 and applied to variable controlled oscillator 103 as a control signal. Here, VCO 103 is used as the local oscillator to mix down signals present in a narrow gigahertz frequency channel while rejecting signals in the adjacent frequency channels.
VCO 103 was implemented using oscillator circuit 200. Oscillator circuit 200 has a bias circuit that includes a current source 205 that is coupled to a current mirror formed by P-channel MOSFETs (Metal-Oxide-Silicon Field Effect Transistors) 201 and 202. The output of the bias circuit is connected to a first lead of spiral inductor 213 and a first lead of spiral inductor 214. A second lead of spiral inductor 213 is connected to a drain of N-channel MOSFET 203 while a second lead of spiral inductor 214 is connected to a drain of N-channel MOSFET 204. The sources of MOSFETs 203 and 204 are connected to ground.
A gate of MOSFET 203 is connected to the drain of MOSFET 204 that is also connected to line VOUT-. A gate of MOSFET 204 is connected to the drain of MOSFET 203 that is also connected to line VOUT+.
Junction varactor 223 is connected between a control voltage line VC from loop filter 102 and the drain of MOSFET 203. Junction varactor 224 is connected between control voltage line VC and the drain of MOSFET 204.
Thus, the two spiral inductors are connected in series, and MOSFETs 203 and 204 are coupled in positive feedback to provide a negative resistance. Junction varactors 223 and 224 function as voltage-controlled capacitors.
The free running oscillation frequency of circuit 200 is determined by the LC tank of circuit 200. The capacitance of the LC tank was reported to be formed by the parasitic capacitance of spiral inductors 213 and 214 to the substrate, the drain-bulk, gate-drain and gate-source capacitances of MOSFETs 203 and 204, and the capacitance of varactors 223, and 224. The sizes of MOSFETs 203 and 204 were a channel length of 0.7 .mu.m and a channel width of 400 .mu.m.
Each varactor was a one picofarad(pf) tunable capacitor. This configuration resulted in about a 1 GHz oscillator with a tuning range as large as 14%. Unfortunately, this range is not sufficient for use in applications such as microprocessors because typically, a microprocessors must operate over a range of frequencies that differ by more than 14%. For example, a power saving mode of a microprocessor can require more than a 14% change in the oscillation frequency.
To meet the range of frequency requirements of a microprocessor, oscillator circuits used in CMOS microprocessors are different from that shown in FIGS. 1 and 2. An example of one microprocessor phase locked loop application is presented in R. Bhagwan and A. Rogers, "A 1 GHz Dual-Loop Microprocessor PLL with Instant Frequency Shifting," 1997 IEEE International Solid-State Circuits Conference, pp. 336, 337 (1997), which is incorporated herein by reference.
The PLL circuit described by Bhagwan and Rogers is used to multiply the frequency of an external clock reference to synthesize a higher-frequency clock signal for the clock distribution networks of the microprocessor. The PLL circuit utilizes a ring oscillator that is made up of a set of gain elements, that each have a signal transition delay, connected in a ring structure. The set of gain elements are typically differential or single-ended transistor inverter stages. A ring oscillator is a typical implementation for microprocessor PLL circuits in general.
Ring oscillators are able to operate over a broad range of frequencies. However, a ring oscillator is sensitive to variations in the power supply voltage. Variations in the power supply voltage contribute to the generation of a significant amount of jitter in the output signal. Since the power supply voltage of a microprocessor is typically very noisy, output jitter is a significant limitation of a ring oscillator.
The problem of output jitter becomes even more pronounced as the operating frequencies of the microprocessors increase, because the clock cycles become shorter. Typically, attempts are made to reduce the output jitter from the ring oscillator by regulating the control signal applied to the oscillator. Unfortunately, the circuitry used to regulate the control circuit becomes more difficult to implement as the power supply voltage levels drop. Consequently, a PLL circuit is needed that has minimal jitter, is insensitive to power supply noise, operates for a variety of power supply levels, and has a wide frequency range.